Until recently, polycrystalline silicon (polysilicon) resistors have been commonly used as load devices in Static Random Access Memories (SRAMs). Stacking polysilicon load resistors above NFETs in the so-called 4D/2R SRAM cells has been advantageously used in the layout of SRAM chips. Devices of this type commonly have the NFETS determine how much real estate is to be consumed, which in turn, determines the cell area. By doing so, a significant reduction in size of the SRAM cell can be achieved. The load resistors of such SRAM cells are formed by resistive polysilicon lands provided by a very thin film or layer of either intrinsic or lightly doped polysilicon. However, because these load resistors must be fairly high-valued, e.g., in the tera-ohm (10E12) range or higher, in order to decrease the current drawn by the cell, the capacity of such SRAM cell chips appears to be limited to 1-Mbit. Beyond this range, the polysilicon layer is so thin that the process tolerances become too difficult to control. In addition, SRAM cells provided with load resistors are highly sensitive to soft errors produced by alpha particles and cosmic rays. Thus, beyond this limit, PFETs that are resistively connected have to be used as load devices instead of polysilicon resistors, in spite of a higher cost and a significantly more complex manufacturing process.
FIG. 1 shows a conventional 6D SRAM cell circuit (referenced 1) with PFETs as load devices. Two cross-coupled NFETs N1 and N2, so-called driver transistors, are connected between common node 2 connected to a first supply voltage V.sub.SS (usually ground, Gnd) and respective nodes 3 and 4, so-called charge storage nodes. Nodes 3 and 4 are in turn connected to a common node 5 tied to a second supply voltage (most commonly, a positive voltage V.sub.CC), respectively, through PFETs P1 and P2. On the other hand, nodes 3 and 4 are also, respectively, tied to bit lines BLT and BLC through NFETs N3 and N4, so-called access transistors. The gate electrodes of NFETs N3 and N4 are attached to the word line WL for READ and WRITE operations.
In view of the complexity of storage nodes 3 and 4, dense CMOS SRAM cells may be obtained in a great variety of manners. For instance, referring to the article entitled: "A 0.1 .mu.A stand-by current ground-bounce-immune 1-M bit CMOS SRAM" by M. Ando et al, published in the IEEE JSSC Vol. 24, N.degree. 6, Dec. 89, pp. 1708-1713, the use of stacked polysilicon gate PFETs (sPFETs) is described, wherein NFET N1 and PFET P1 share the same gate electrode. This technique combined with a 0.8 .mu.m twin-well CMOS process results in a small memory cell size of 41 .mu.m.sup.2. The advantages and disadvantages of this approach are analyzed in the European Patent EP-A-90480109.9, filed on 31 July 1990, and of common assignee.
Another technique which takes advantage that NFET N1 and PFET P2 have their respective drain region and gate electrode at the same potential, is described in the article entitled: "TFT cell technology for 4M bit and more high density SRAMs" by M. Kinugawa et al, published in the IEEE 1990 Symposium on VLSI Technology 4.3, pages 23-24. FIG. 2 of the present application reproduces FIG. 7 of this article. It shows a partial cross-section view of the 6D SRAM cell circuit of FIG. 1, when it is integrated in a semiconductor substrate according to the CMOS manufacturing process described therein. The PFETs used as load devices, and fabricated with this thin-film manufacturing process will be referred henceforth as iPFETs, because of their upside-down or inverted design. The structure 6 is a good example of the most advanced state of the art known to date claiming a memory cell size of 20.3 .mu.m.sup.2, for a 0.5 .mu.m CMOS process. In FIG. 2, numeral 7 indicates the P type silicon substrate. Numerals 8 indicate the different field recess oxide (ROX) regions that are used to isolate the various active regions of the structure. Numerals 9 are generically active N+ implanted source and drain regions of the NFETs, although some of these regions can also be used as gate electrodes for the iPFETs.
FIG. 2 refers, more particularly, to the FET devices N2 and P2 shown in FIG. 1. Numeral 10 indicates the gate dielectric layer, typically an SiO.sub.2 layer, which forms the gate dielectric of the bulk FET devices, i.e., the NFETs and PFETs formed in the substrate by the CMOS manufacturing process. The tungsten polycide layer 11 results from alloying highly doped N+ polysilicon with tungsten. Layer 11 is patterned to delineate the gate electrodes of the bulk FET devices. Gate electrodes of NFETs N2 and N1, respectively referenced 11-1, 11-2, and 11-3, designate the gate electrode of a non-referenced FET device in FIG. 1. Gate electrode 11-2 forms a buried contact with region 9-2 which becomes the drain region DN2 of NFET N2. SiO.sub.2 layer 12 forms the gate dielectric of the iPFETs and coats gate electrodes 11-1, 11-2 (partially) and 11-3. N+ doped region 9-3 plays both the role of the gate electrode GP2 of iPFET P2 (oxide layer 12 is the gate dielectric thereof) and the drain region DN1 of NFET N1. A polysilicon land 13-1 coats gate electrodes 9-3 and 11-3, and, is isolated therefrom by an SiO.sub.2 layer (12). Polysilicon land 13-1 results from the patterning and selective doping of a lightly P-doped polysilicon layer 13 (the doping is performed by adjusting the voltage threshold VT of the iPFETs) that was deposited and recrystallized to form the body of the iPFETs. As apparent from FIG. 2, this polysilicon land 13-1 is highly doped with a P-type dopant except on the region 9-3 just above N+. The lightly doped portion of land 13-1 forms the channel region of the iPFET P2, while the adjacent highly P+ doped regions form the source and drain regions thereof, respectively referred to as SP2 and DP2. An extension of the drain region of iPFET P2 in polysilicon land 13-1, referred henceforth as the extended drain region EDP2, contacts the small portion of gate electrode 11-2 which is exposed through an opening in the oxide layer 12. More generally, an oxide layer 12 is opened for each cell, at all locations where it is required to make contact between the N+ doped polysilicon gate electrode of a NFET and the adjacent P+ extended drain region of the corresponding iPFET. Note that N+ region 9-2, gate electrode 11-2 of NFET N1 and the extended drain region of iPFET P2 in land 13-1, are at the source potential of node 4, thereby achieving the desired cross-coupling of the devices, as illustrated in the cell circuit of FIG. 1. At this stage of the process, the structure is said to have completed the Master Slice processing steps of a polysilicon gate CMOS FET technology, i.e., the bulk and thin-film FET devices have been fabricated in the substrate. The structure is passivated by a relatively thick insulating SiO.sub.2 layer 14 of about 500 nm. As such, the structure completes the FEOL (Front End Of the Line) processing.
Elements that will now be described are formed during the personalization steps or BEOL (Back End Of the Line) processing. Tungsten polycide lands 15-1, 15-2 and 15-3 result from patterning a tungsten polycide layer 15. Referring to FIG. 2, the polycide land 15-1, which connects an N+ active region 9-1 (the source region of NFET N2) to ground will be referred to hereinafter as the Gnd bus. An additional insulating SiO.sub.2 layer 16 completes the structure. The insulating layer 16 is provided with contact openings to allow appropriate contacting of metal bit lines BLT and BLC with the power busses (e.g., the V.sub.CC power bus) that are obtained after patterning an aluminum-silicium (Al-Si) layer 17. The structure is passivated with SiO.sub.2 layer 18. An additional second aluminum layer 19 is shown on top of the structure. All succeeding layers, in particular polysilicon layer 13, are conformally deposited. As a result, the upper layers of structure 6 display a typical "corrugated" or "castellated" relief aspect.
The cell construction of FIG. 2, wherein the iPFETs are used as load devices is of great interest in terms of density, in view of the fact that the cell area is substantially determined by the area of the bulk NFETs. However, the semiconductor structure and corresponding manufacturing process disclosed present major disadvantages which are recited hereinafter, and which result in significant potential problems.
1. In order to manufacture the structure of FIG. 2, six additional masks are required with respect to a conventional manufacturing process of 6D SRAM cell chips not offering iPFETs in the menu. The first mask is used to partially remove the gate oxide layer 10 above the source region 9-2 of NFET N2, which establishes a buried contact between gate electrode 11-2 and region 9-2. The second mask provides an opening in layer 12 above gate electrode 11-2. The third mask is used to pattern the P-type lightly doped polysilicon layer 13 to shape the desired polysilicon land 13-1, wherein the body of iPFET P2 and its related extended drain region (for connection with underlying gate electrode 11-2) are formed. The fourth mask is a block-out mask that is required to protect the channel region of iPFET P2 body from the implant of P-type dopants to form the highly doped P+ source and drain regions thereof. An extended drain region is formed at this stage of the process. The fifth mask defines contact openings in layer 14 where polycide lands, e.g., 15-1, to convey the Gnd potential, and establish contact with source regions 9 of selected NFETs, e.g., the source region SN2 of NFET N2 (FIG. 2). Finally, the sixth mask delineates the polycide lands, e.g., 15-1, the word lines and power busses. PA0 2. Region 9-3 is the drain region DN1 of NFET N1 and the gate electrode GP2 of iPFET P2. Thus, the layouts of these two devices are strongly interdependent both in terms of device size and device layout which, in turn, results in less flexibility in their respective design. More generally, since the width of diffusion regions 9-1, . . . of the driver NFETs, e.g., N1, must be at the minimum allowed by the technology for maximum density, the gate length of the iPFETs, e.g., P2, is thus determined. This constitutes a potential source of reliability hazards. In particular, if the out-diffusion of the P+ dopants contained in the implanted source and drain regions of iPFET P2 is not well controlled, the source and drain regions SP2 and DP2 become too large, thereby reducing the effective channel length of iPFET P2. As a result, punch-through problems can sometimes occur. The channel length of iPFET P2 cannot be increased (if maximum density is sought) since this length is dictated by the performance requirements of NFET N1. PA0 3. The structure of iPFET P2 illustrated in FIG. 2 is upside-down, thus self-alignment registration (SAR) is not possible. Since the block-out mask defining the channel region of iPFET P2 is at the minimum image size, alignment tolerance between this block-out mask and the channel region can result in a channel region not correctly aligned with the gate electrode. FIGS. 3A and 3B are enlarged views of the portion of structure 6 which more particularly shows iPFET P2, and which illustrates the effect of such a misalignment on the electrical characteristics thereof. This effect mainly consists in a parasitic resistor added to an ideal PFET P that would have been obtained if no misregistration had existed. This effect will now be explained in more detail. For both cases (positive and negative misalignment) shown in the upper part of FIGS. 3A and 3B, a high value resistor R is placed in series with the drain or source region of the ideal PFET P. This is illustrated in the lower part of FIGS. 3A and 3B, wherein a schematic of the electrical is shown. This parasitic resistor decreases the effective gate to source overdrive voltage (VGS-VT) of iPFET P2 (which has already a high threshold voltage VT) and hence also decreases its "ON" current. Finally, in the case of misalignment, the iPFET P2 is far from an ideal PFET P. Additionally, due to their upside-down construction, iPFETs cannot be provided with improved source/drain structures such as LDD (Lightly Doped Drain). This potentially may be a problem, because the effective length of the iPFETs is highly sensitive to the source/drain dopant out-diffusion as was previously mentioned, and which is admittedly difficult to maintain low in polysilicon. PA0 4. Since the iPFETs are formed after the bulk devices have been completed, the thermal budget necessary to polysilicon recrystallization and source/drain dopants reactivation must be kept to a low. This limitation is necessary to minimize the impact of these steps on the bulk FET devices and on the underlying tungsten polycide layer forming gate electrodes 11-1, . . . It is also a further limitation on improving the iPFET performance. PA0 5. The gate electrode of the iPFET P2 has no optimized work function. Since the iPFET P2 gate electrode is formed by the N+ drain region of a driver transistor, e.g., NFET N1, there is no flexibility in selecting the type of conductivity of the gate electrode. The gate electrode of the iPFET is N+ type, whereas P+ type would have been preferred. It is well recognized that this situation creates punch-through problems. In particular, punch-through effects induce leakage currents which are critical to the standby power consumption of the SRAM cell. PA0 6. As previously mentioned in conjunction with FIG. 2, the conventional manufacturing process results in a non planarized structure 6. The gate oxide layer 12 and the polysilicon layer 13 forming iPFET P2 are deposited over the "castellated" topology of gate electrodes 11-1, 11-2, 11-3, . . . albeit slightly smoothed by the SiO.sub.2 layer 12. A non-planar topology causes reliability problems, known as "step coverage", caused by a polysilicon layer 13 which is much thinner than the polysilicon layer 11 forming the gate electrodes. PA0 7. A parasitic P+/N+ diode (referenced D) in FIGS. 3A and 3B is formed between the N+ gate electrode 11-2 of NFET N1 and the P+ extended drain region of iPFET P2. This diode degrades the quality of the contact, which is no longer of an ohmic type, thereby slowing down the overall performance of the SRAM cell. PA0 8. The power busses and possibly the local interconnect scheme that makes straps and short distance connections at the silicon wafer level, are all made of polycide. Tungsten polycide is a good conductive material and is known to exhibit higher resistivity than metals. PA0 a) providing a P-type silicon substrate having a surface that includes a plurality of isolation regions; PA0 b) delineating polysilicon lands at selected isolation regions; PA0 c) forming N-well regions into the substrate at a location where bulk PFETs are to be subsequently formed; PA0 d) forming insulator encapsulated conductive polysilicon studs to provide gate electrodes at selected locations of the structure; PA0 e) forming self-aligned source/drain regions of the bulk NFETs into the substrate; PA0 f) forming self-aligned source/drain regions of the bulk PFETs and pPFETs into the substrate and into the polysilicon lands, respectively; and PA0 g) forming contact regions to the selected locations that include the source/drain regions. PA0 h) exposing the top of certain polysilicon studs; PA0 i) blanket depositing an etch stop layer onto the structure; PA0 j) forming an insulating matrix provided with openings onto the structure exposing desired locations of the underlying etch stop layer; PA0 k) etching the exposed regions of the etch stop layer; and PA0 l) filling the openings of the matrix with conductive material to form contact studs. PA0 m) forming an etch stop layer over selected polysilicon studs and selected regions of the substrate to facilitate the subsequent formation of overpass conductors. PA0 1. Only three or four additional masks are required; in the latter case, the method allows implementing useful overpass conductors. PA0 2. The pPFET size and layout are independent of the underlying bulk NFET size and layout. PA0 3. The pPFET benefits from the engineering done for bulk FET devices, e.g., the source/drain are self-aligned with the gate electrode, thereby obtaining LDD structures. Finally, a short channel length is achievable in spite of the fast out-diffusion of dopants in polysilicon. PA0 4. No constraint on thermal budget associated with the pPFET exists since the polysilicon layer forming the "body" thereof is deposited and recrystallized prior to the process steps necessary to fabricate the bulk FET devices. On the other hand, the source/drain dopants reactivation of the pFETs is simultaneously performed with the bulk FET devices. PA0 5. The pPFET is controlled by a tungsten polycide gate electrode for optimized work function. PA0 6. The pPFET is formed onto a planarized surface. PA0 7. The N+/P+ diode contact structure is replaced with a tungsten contact stud which provides excellent ohmic contact. PA0 8. Word lines WL, Gnd and V.sub.CC power busses, and local interconnect conductors are made of metal instead of tungsten polycide.
The above cited problems are favorably resolved by the manufacturing method of the present invention and the resulting integrated circuit structures thereof.